VHDL NAND gate CODE and waveform

 

Implementation of  the NAND  logic gates in VHDL using Data Flow Architecture using MAX +2.

VHDL Code

library IEEE;

use IEEE.Std_Logic_1164.all;

entity nand_gate is

port(A : in std_logic;

         B : in std_logic;

         C : out std_logic);

end nand_gate;

 

architecture nandLogic of nand_gate is

begin

C <= A nand B;

end nandLogic;

 Logic diagram of nand gate

Waveform of nand gate in max plus 2

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