VHDL not gate Code

NOT GATE PROGRAM ON MAX PLUS 2 

Here is the simple program  of not gate on altera max + 2,  how to compile and how to simulate the not gate code.
 
so let's begin,

Implementation of  NOT  logic gates in VHDL using Data Flow Architecture using MAX +2.

VHDL Code

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Library IEEE;

use IEEE.Std_Logic_1164.all;

entity not_gate is

port(A : in std_logic;

             C : out std_logic);

end not_gate;

 

architecture notLogic of not_gate is

begin

C <= not A;

end notLogic;

 ////////////////////////////////////////

Logic diagram of Not  gate

 NoT Gate

Waveform of not gate in Max +2.

For more help please watch my youtube video for better understand..

IN THIS VIDEO YOU CAN EASILY LEARN THE WORKING OF MAX +2.


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